High Speed Power Efficient Dynamic Comparator with Low Power Dissipation and Low Offset

Abstract

When designing digital circuits with high speeds, dynamic comparators are necessary. In particular, central processing units (CPUs) in a wide variety of electronic devices rely on low-power, high-speed dynamic comparators. Numerous comparators, which are comparison circuits, make up these central processing units. This research article introduces a low-voltage, low-power Double Tail Dynamic Comparator (DTDC) that uses less power than previous designs. This journal article compares and contrasts the suggested design with several kinds of dynamic comparators. The suggested architecture is contrasted with dynamic comparators that rely on techniques such as regenerative latch, floating inverter amplifier, and Double Tail. The Tanner EDA simulation program is used to model this design using 18nm technology. This suggested design use the self-biasing approach to execute the pre-amplification process. This suggested design operates with less kick back noise thanks to the self-biasing mechanism.